Freescale Semiconductor /MK53DZ10 /LCD /GCR

LCD duty select

0 (000): Use 1 BP (1/1 duty cycle).

1 (001): Use 2 BP (1/2 duty cycle).

2 (010): Use 3 BP (1/3 duty cycle).

3 (011): Use 4 BP (1/4 duty cycle). (Default)

4 (100): Use 5 BP (1/5 duty cycle).

5 (101): Use 6 BP (1/6 duty cycle).

6 (110): Use 7 BP (1/7 duty cycle).

7 (111): Use 8 BP (1/8 duty cycle).

LCD clock prescaler

LCD clock source select

0 (0): Selects the default clock as the LCD clock source.

1 (1): Selects the alternate clock as the LCD clock source.

LCD driver enable

0 (0): All frontplane and backplane pins are disabled. The LCD controller system is also disabled, and all LCD waveform generation clocks are stopped. VLL3 is connected to VDD internally.

1 (1): LCD controller driver system is enabled, and frontplane and backplane waveforms are generated. All LCD pins, LCD_Pn, enabled using the LCD pin enable register, output an LCD driver waveform.The backplane pins output an LCD driver backplane waveform based on the settings of DUTY[2:0]. Charge pump or resistor bias is enabled.

LCD driver, charge pump, resistor bias network, and voltage regulator while in Stop mode.

0 (0): Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode.

1 (1): Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU goes into Stop mode.

LCD driver, charge pump, resistor bias network, and voltage regulator stop while in Wait mode.

0 (0): Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Wait mode.

1 (1): Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU goes into Wait mode.

LCD alternate clock divider

0 (0): Divide factor = 1 (No divide)

1 (1): Divide factor = 8

LCD fault detection complete interrupt enable

0 (0): No interrupt request is generated by this event.

1 (1): When a fault is detected and FDCF bit is set, this event causes an interrupt request.

LCD frame frequency interrupt enable

0 (0): No interrupt request is generated by this event.

1 (1): When LCDIF bit is set, this event causes an interrupt request.

Voltage supply control

0 (00): Drive VLL2 internally from VDD.

1 (01): Drive VLL3 internally from VDD.

3 (11): Drive VLL3 externally from VDD or drive VLL1 internally from VIREG.

Load adjust

High reference select

0 (0): Divide input, VIREG = 1.0 V for 3 V glass.

1 (1): Do not divide the input, VIREG = 1.67 V for 5 V glass.

Charge pump or resistor bias select

0 (0): LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)

1 (1): LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)

Regulated voltage trim

Regulated voltage enable

0 (0): Regulated voltage disabled.

1 (1): Regulated voltage enabled.